Target voltage generator for a dc to dc converter, a combination of a target voltage generator  and a dc to dc converter, and a method of operating a dc to dc converter

ABSTRACT

A target voltage generator for use with a DC to DC converter, the DC to DC converter having a first input for receiving a voltage to be converted, an output for outputting a converted voltage, a first reference voltage input for receiving a first reference voltage and a controller arranged to compare the output voltage of the DC to DC converter with the first reference voltage and to modify the operation of the DC to DC converter so as to reduce a difference between the output voltage and the first reference voltage; the target voltage generator comprising a circuit arranged to compare the output voltage of the DC to DC converter with a second reference voltage and to use a result of the comparison to generate or modify the first reference voltage.

FIELD OF THE INVENTION

The present invention relates to a target voltage generator for use witha switching DC to DC converter, to a combination of a target voltagegenerator and a switching converter, and to a method of operating aswitching converter.

BACKGROUND

Switching converters in which transistor switches are driven betweenfully on and fully off provide great efficiency improvements overdissipative style converters in which a transistor is used in a linearmode to drop a voltage across the transistor while current flows throughthe transistor such that a voltage at a terminal thereof, such as anemitter, collector or source or drain of the transistor is held at adesired output voltage. However, switching converters can exhibitdegraded output voltage regulation under certain circumstances.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda target voltage generator for use with a DC to DC converter, the DC toDC converter having a first input for receiving a voltage to beconverted, an output for outputting a converted voltage, a firstreference voltage input for receiving a first reference voltage and acontroller arranged to compare the output voltage of the DC to DCconverter with the first reference voltage and to modify the operationof the DC to DC converter so as to reduce a difference between theoutput voltage and the first reference voltage. The target voltagegenerator comprises a circuit arranged to compare the output voltage ofthe DC to DC converter with a second reference voltage and to use aresult of the comparison to generate or modify the first referencevoltage.

It is thus possible to modify a target voltage supplied to a DC to DCconverter so as compensate for performance degradation within a switchedmode converter.

The controller may be associated with a buck converter (step down), aboost converter (step up) or a buck-boost converter.

According to a second aspect of the present invention there is provideda DC to DC converter, comprising: a DC to DC pulse width modulatedvoltage converter having a first control loop for comparing an outputvoltage with a first reference voltage; and a second control loop havinga response time which is slower than a response time of the firstcontrol loop, said second control loop being arranged to compare theoutput voltage with a second reference voltage and as a result of thatcomparison to modify the first reference voltage.

According to a third aspect of the present invention there is provided amethod of operating a DC to DC converter, where said converter isarranged to compare a DC to DC converter output voltage with a firstreference voltage, and to modify its operation as a result of thecomparison, the method comprising comparing the DC to DC converteroutput voltage with a second reference voltage, and using the result ofthe comparison to generate or modify the first reference voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will now be described, in a non-limiting manner,with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a DC to DC converter in association withan embodiment of a reference voltage generator;

FIG. 2 is a circuit diagram showing an example of a switched mode buckconverter in greater detail;

FIG. 3 shows a current waveform (solid line) and output voltage(chain-dot line) for a buck converter;

FIG. 4 is a circuit diagram of a first embodiment of a target voltagegenerator;

FIG. 5 is a circuit diagram of a second embodiment of a target voltagegenerator; and

FIG. 6 is a circuit diagram showing a modification to part of thecircuit shown in FIG. 4.

DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG. 1 is a circuit diagram of a DC-DC converter, generally designated2. The DC-DC converter of FIG. 1 is a buck converter, also known as abuck regulator, which receives a first potential difference between afirst input node 4 and a second input node 6, and which outputs areduced voltage difference between an output node 8 and the second inputnode 6.

A buck regulator is often used with battery powered equipment where, forexample, an anode of a battery or battery array is connected to thefirst input node 4 and the cathode of the battery or battery array isconnected to the second input node 6. Typically, because the voltages inan item of battery powered equipment can float with respect to earth, itis convenient to regard the battery cathode as defining a local 0 Vreference or a local ground.

The DC to DC converter 2 may be a known switching converter. Such aconverter may have an embedded or associated controller 10, shown inFIG. 1 as being internal to the DC to DC converter 2 which receives areference voltage, which herein will be referred to as a first referencevoltage, at a first reference voltage input node 12. The controller 10also receives the output voltage from the output node 8 at a feedbacknode 14, and as a result of comparing the first reference voltage withthe output voltage, it implements one of several known control schemesto maintain the output voltage as a desired value.

These control schemes are generally well behaved when the differencebetween the first potential, (the input voltage) and the output voltageis within a certain operating range specific to the implementation ofthe DC to DC converter, and/or when the load current from the converteris within a specific operating range. In these instances the specificoperating ranges are within the minimum to maximum input voltage range,and within the minimum to maximum load current range for which the DC toDC converter was designed.

However, unlike the prior art converters or regulators, the circuit ofFIG. 1 further includes a reference voltage generator 20 which receivesa second reference voltage at a second reference voltage input 22. Thesecond reference voltage may be provided by a precision voltage source24. A second input 26 of the reference voltage generator 20 forms anestimate of the error between the second reference voltage and the DC toDC converter output voltage, and this estimate of error is used togenerate the first reference voltage which is supplied by the referencevoltage generator 20 to the first reference voltage input node 12 of theDC to DC converter 2.

In order to understand why it is desirable to provide the referencevoltage generator 20, rather than connecting the precision voltagereference source 24 directly to the first reference voltage input 12, itis helpful to briefly consider the operation of a DC to DC switchingconverter.

FIG. 2 shows the internal configuration of a buck converter. It shouldbe noted that the invention is not limited to use with buck convertersand the concepts and embodiments described herein can be used with boostconverters and buck-boost converters. A first electrically controlledswitch 30, which can be regarded as being a high side switch, isconnected between the first input node 4 and a common node 32. A firstend of an inductor 34 is connected to the common node 32. A second endof the inductor is connected to the output node 8. The firstelectrically controlled switch 30 is responsive to a first switchcontrol signal Si provided by the controller 10.

A second electrically controlled switch 40, which can be regarded as alow side switch, is connected between the common mode 32 and the secondinput node 6. The second electrically controlled switch 40 is responsiveto a second switch control signal S2 provided by the controller 10.

The controller 10 has an “output voltage” input V_(out) connected to theoutput node 8. The controller, in use, acts to compare the outputvoltage at node 8 with a first reference voltage, V_(ref), which isprovided at a first reference voltage input 12 of the controller 10.

Suppose the voltage at the first input terminal 4 is V1, the voltage atthe second input terminal 6 is V2 and the output voltage at the outputnode is V_(out).

In use V1>V_(out), and V_(out)>V2.

The controller 10 is arranged to operate the first switch 30 and thesecond switch 40 in a pulse width modulated manner so as to successivelybuild and then reduce current flow in the inductor 34.

In a first phase, which can be regarded as a current build phase, thefirst switch 30 is closed.

The voltage V_(ind) across the inductor 34 is approximately:

V_(ind)≈V1−V_(out)   equation 1

And the rate of increase in current within the inductor 34, having aninductance L is approximately

$\begin{matrix}{\frac{I}{t} \approx \frac{\left( {{V\; 1} - V_{out}} \right)}{L}} & {{equation}\mspace{14mu} 2}\end{matrix}$

The current flows for a time t1, as shown in FIG. 3 by curve 50, duringwhich it rises from a value I1 to I2, towards the output node 8. Some ofthe current exits the output node 8 to supply a load 9 connected to theoutput node.

Returning to FIG. 2, it can be seen that a capacitor 44 is connectedbetween the output node 8 and the second input node 6. This acts as areservoir capacitor to accept and store some of the charge.

The change in voltage at the capacitor C can be approximated as:

$\begin{matrix}{{\Delta \; V_{out}} \approx {\int_{0}^{t_{1}}{\frac{i_{capacitor}}{C}{t}}}} & {{equation}\mspace{14mu} 3}\end{matrix}$

where i_(capacitor) is the amount of current that flows from theinductor 34 into the capacitor 44, and C is the capacitance of thecapacitor.

The controller 10 may, for example, be a hysteretic controller whichacts to keep the first switch 10 conducting until such time as V_(out)has risen to an upper threshold V_(H). It should however be noted thatthe nature of the controller or control scheme used to implement thepulse width modulation is not relevant to the present invention, and anysuitable controller such as constant on or off time controllers, peakcurrent mode or valley current mode or voltage mode controllers may beused. However, for ease of discussion, it will be assumed that thecontroller operates as a hysteretic controller and that the currentdrawn by the load is greater than a first current threshold, as often DCto DC converters are operable in a low power mode when the load currentdrops to a low value.

Once V_(out) has risen to its upper threshold V_(H), the controller 10opens the first switch 30. After a brief delay to ensure that the firstswitch has become high impedance, the controller closes the secondswitch 40, thereby marking the commencement of a second phase in whichthe current in the inductor is reduced, and bringing the voltage at thefirst end of the inductor down to V2. In fact, it should be noted thatsince the current that had built in the coil during the first phase nowflows through the second switch 40, there will be a small voltagedropped across the second switch 40. This small voltage drop isinsignificant in terms of its impact on the analysis presented here, butit should be noted that this voltage drop can be exploited to measurethe current magnitude and direction of current flow if desired.

During the second phase, the voltage across the inductor 34 can bewritten as

V _(ind) =V2−V _(out)   equation 4

And the change in inductor current is

$\begin{matrix}{\frac{I}{t} = \frac{{V\; 2} - V_{out}}{L}} & {{equation}\mspace{14mu} 5}\end{matrix}$

Since V2 is less than

$V_{out},\frac{I}{t}$

is negative and the current in the inductor starts to reduce, asindicated in FIG. 3 by line 51 with the inductor current reducing fromI2 to I1 in a period t2.

If, as is often the case, V_(out) is much closer to one of V1 and V2than the other one of V1 and V2, then the rates of current build andcurrent decay are significantly different. The current waveform shown inFIG. 3 is indicative of a system where V_(out) is much closer to V1 thanit is to V2.

During the period from time t0 to time t1 some of the inductor currentflows to the load. Further analysis reveals that at the moment the firstswitch 30 was switched off, the current in the inductor 34 wassufficient to meet the demand of the load 9 and to be charging thecapacitor 44 so as to increase the voltage on the capacitor.

When the second switch 40 is turned on, the magnitude of the current is,to a first approximation, unchanged, so the output voltage V_(out)briefly continues to rise until such time as the inductor currentreduces to become less than the load current, and as a consequence thecapacitor 44 starts to supply current to the load. The voltage on thecapacitor starts to fall, and the controller 10 is responsive to this,and keeps the second switch 40 in a conducting state until such time asthe output voltage V_(out) has fallen to a lower threshold value V_(L).

Once V_(L) is reached, at time t2, the second switch 40 is made highimpedance. The high side (first) switch 30 is closed, but there is adelay between this occurring and the current building to a level thatstops some of the current to the load being supplied from the capacitor.Therefore, initially the voltage continues to fall. The time period t0to t2 represents the duration of one control cycle of the DC-DCconverter. Once one, i.e. Nth, control cycle has completed, asubsequent, N+1th, control cycle is commenced by the controller 10opening the first switch 30 to cause current to build in the inductor.

The evolution of V_(out) with respect to time for the scenario describedabove is shown in FIG. 3 by chain-dot curve 52.

In such a hysteretic control scheme the duration of each control cycle,and hence the switching frequency of the DC-DC converter, can becontrolled by the difference between V_(H) and V_(L). This differencecan be regarded as a hysteresis, and such a control scheme as describedhere is a hysteresis control scheme (or hysteretic control scheme).

The first and second switches 30 and 40 may have to operate vary rapidly(as a function of the PWM duty cycle and the switching frequency), andare often implemented as field effect transistors. For example when theload is drawing a relatively large current, the duration for which thesecond switch is conducting may be short. Put another way the durationfor which the switch is on, which will be referred to as the switch “on”time may start to become comparable with the propagation delays withinthe controller. A similar problem may occur when the output is verylightly loaded.

These short “on” and “off” times, may start to become comparable withthe sum of the comparator decision time, propagation delay in thecontrol logic, and transistor switching times (which may vary betweendevices and with input voltage) and may give rise to unquantifiabledegradation in performance. Much of the problem is addressed by thecontrol loop within the controller 10 of the DC to DC converter 2.However there is an inherent trade off in controller performance becausethe controller needs to balance the needs of stability and voltageregulation against the need to be highly responsive to rapidly changingload currents drawn by the load.

Known DC to DC converters may include an error amplifier which amplifiesthe difference between the first reference voltage and the outputvoltage. Errors introduced by this error amplifier, the comparator andthe switching logic and switches are effectively divided by the gain ofthe error amplifier when referenced to the output of the DC to DCconverter. The error amplifier may be used to implement a low frequencypole, as this gives improved voltage regulation under steady stateconditions, but at the expense of control loop bandwidth and henceresponsiveness to step changes in load current.

The embodiment shown in FIG. 1 has the advantage that the feedback loopis effectively broken into two substantially independent feedback loops,although in topological terms they can be regarded as being nested. Thismeans that the controller 10 of the DC to DC converter can be biasedtowards giving a good transient response. The second feedback loopformed by the reference voltage generator can be much slower, and bedesigned to achieve good regulation, and can compensate for delays inthe switching circuits of the DC to DC converter, even when it isheavily loaded.

The second feedback loop is provided by a target voltage generator, anexample of which will now be described with reference to FIG. 4.

The target voltage generator 20 comprises an input circuit, generallydesignated 82 which receives the output voltage of the DC to DCconverter, and scales it if necessary using a potential divider formedby resistors 84 and 86 connected in series between an input node 88 anda local ground 90. The scaled feed-back voltage VFB may then be low passfiltered by a resistor and capacitor filter generally designated 92 soas to remove short term variations due to load transients or noise fromthe scaled feedback signal. The scaled feedback signal is, in theembodiment illustrated in FIG. 4 compared with a second referencevoltage VREF2 from the precision voltage source 24 by a comparator 100.The scaled feedback signal is provided to a first input 102, such as aninverting input of the comparator 100 while a second reference voltagefrom the reference voltage generator 24 is provided to a second input ofthe comparator 100. An output of the comparator 100 is provided to aup/down control input of an up/down counter 110. The counter 110 isclocked at a relatively slow clock rate by a slow clock 112 such thatthe counter only updates periodically, and counts up if VFB is less thanthe second voltage reference VREF2, and counts down if VFB is greaterthan VREF2. The action of the counter is to integrate the output of thecomparator 100 and in so doing the counter will get to a state where, ifVout is stable and unchanging, the value of the counter would ditherabout a value. The output of the counter is provided as an input to adigital to analog converter 120 which, in this embodiment, outputs avalue VREF-LOCAL which acts as a voltage reference, i.e. the firstreference voltage, used by the switched mode converter. Thus as theswitching rate of the switched mode converter or the on and off time ofthe transistors vary such that propagation delays within the converterintroduce unquantified voltage errors within the controller of theswitched mode converter, the reference voltage generator integratesthose errors and modifies the reference voltage supplied to the DC to DCconverter so as to bring the output voltage thereof back towards thetarget voltage.

The counter 110 may be provided in association with an initializationcircuit (not shown) to preload the counter to an initial value of VREF(the first reference voltage) at power up.

In an example, a DC to DC converter may have a first control loop withan open loop bandwidth around 15 to 20 or times slower than theconverter switching frequency. Thus a converter having a switchingfrequency of 3 MHz may have an open loop bandwidth of around 180 kHz.The slow clock 112 may be set to be significantly slower than the openloop bandwidth, for example around 12 kHz (which is around 1/256 of theswitching frequency as frequency division by powers of two is generallyeasy to implement). The DAC 120 may have a least significant bit size ofless than 1%, for example of around 0.1%, of the reference voltagevalue. Thus the changes made are generally slow compared to the speed ofthe control loop provided by the controller 10, and small compared tothe reference voltage.

In an alternative embodiment, as shown in FIG. 5 the output of the DAC120 may be combined with VREF2 by a summer 130. The summer may form aweighted average of VREF2 and the output of the DAC 120. Thisarrangement ensures that the first reference voltage always has aninitial value close to VREF2. Additionally the changes made by the DAC120 are relatively small steps, so the controller 10 does not becomeexcessively perturbed by a change in the DAC output.

The target voltage generator may also be implemented in the analogdomain as shown in FIG. 6.

In FIG. 6 the up/down counter 110 and the DAC 120 have been replaced byan integrator formed by a capacitor 140 placed in the feedback looparound an operational amplifier 142. The operational amplifier 142 iscoupled to the output of the comparator 100 by a resistor 144 whichrestricts a rate of charge transfer of the capacitor 140.

It is thus possible to modify a known DC to DC converter and itscontroller by the provision of a reference voltage generator which canadapt a reference voltage supplied to the controller of the DC to DCconverter so as to improve regulation at the output of the converterwithout compromising its responsiveness to load changes.

The claims presented herewith are in single dependency format. However,it is to be understood that the use of single dependency format was onlyadopted to comply with claims fee structures at the USPTO, and that forother jurisdictions each claim can be multiply dependent on anypreceding claim (except where this is clearly not feasible) of the samecategory.

1. A target voltage generator for use with a DC to DC converter, the DCto DC converter having a first input for receiving a voltage to beconverted, an output for outputting a converted voltage, a firstreference voltage input for receiving a first reference voltage and acontroller arranged to compare the output voltage of the DC to DCconverter with the first reference voltage and to modify the operationof the DC to DC converter so as to reduce a difference between theoutput voltage and the first reference voltage; the target voltagegenerator comprising a circuit arranged to compare the output voltage ofthe DC to DC converter with a second reference voltage and to use aresult of the comparison to generate or modify the first referencevoltage.
 2. A target voltage generator as claimed in claim 1, in whichthe target voltage generator comprises means for comparing the outputvoltage with the second reference voltage and integrating a result ofthe comparison.
 3. A target voltage generator as claimed in claim 2, inwhich the target voltage generator comprises a comparator for comparingthe output voltage with the second reference voltage.
 4. A targetvoltage generator as claimed in claim 1, comprising an integrator forintegrating the result of the comparison.
 5. A target voltage generatoras claimed in claim 4, in which the integrator is an analog integrator.6. A target voltage generator as claimed in claim 4, in which theintegrator is a digital integrator.
 7. A target voltage generator asclaimed in claim 4, in which the integrator comprises an up/downcounter, and the counter is counted up in response to a first outputstate of the comparator and counted down in response to a second outputstate of the comparator.
 8. A target voltage generator as claimed inclaim 7, in which a clock rate of a clock used to clock the counter isset so as to provide a response rate of the target voltage generatorwhich is slower than a response rate of the controller of the DC to DCconverter.
 9. A target voltage generator as claimed in claim 8, in whicha response rate of the target voltage generator is at least ten timesslower than the response rate of the controller of the DC to DCconverter.
 10. A target voltage generator as claimed in claim 7, furthercomprising an analog to digital converter responsive to an output of thecounter for generating the first reference voltage.
 11. A target voltagegenerator as claimed in claim 10, further comprising an initialisationcircuit for setting the counter to an initial value.
 12. A targetvoltage generator as claimed in claim 7, further comprising an analog todigital converter responsive to the output of the counter for generatinga modification voltage to be added to the second reference voltage so asto generate the first reference voltage.
 13. A DC to DC converter incombination with a target voltage generator as claimed in claim
 1. 14. ADC to DC converter, comprising: a DC to DC pulse width modulated voltageconverter having a first control loop for comparing an output voltagewith a first reference voltage; and a second control loop having aresponse time which is slower than a response time of the first controlloop, said second control loop being arranged to compare the outputvoltage with a second reference voltage and as a result of thatcomparison to modify the first reference voltage.
 15. A DC to DCconverter as claimed in claim 14, in which the second control loopcomprises means for comparing the output voltage and the secondreference voltage so as to determine at least the sign of an error therebetween, and means to process the error so as to generate a firstreference voltage or a correction to the first reference voltage.
 16. ADC to DC converter as claimed in claim 14, in which the response time ofthe second control loop is at least five times slower than the responsetime of the first control loop.
 17. A method of operating a DC to DCconverter, where said converter is arranged to compare a DC to DCconverter output voltage with a first reference voltage, and to modifyits operation as a result of the comparison, the method comprisingcomparing the DC to DC converter output voltage with a second referencevoltage, and using the result of the comparison to generate or modifythe first reference voltage.
 18. A method as claimed in claim 17, inwhich the act of comparing the output voltage with the second referencevoltage comprises determining a sign of a difference, and periodicallymaking a increase or decrease to the second reference voltage based onthe sign of the difference.